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?2008 integrated device technology, inc. october 2008 dsc-2691/13 1 high speed 2k x 8 dual-port static ram with interrupts idt71321sa/la idt71421sa/la features high-speed access ? commercial: 20/25/35/55ns (max.) ? industrial: 25/55ns (max.) low-power operation ? idt71321/idt71421sa ? active: 325mw (typ.) ? standby: 5mw (typ.) ? idt71321/421la ? active: 325mw (typ.) ? standby: 1mw (typ.) two int flags for port-to-port communications functional block diagram notes: 1. idt71321 (master): busy is open drain output and requires pullup resistor of 270 ? . idt71421 (slave): busy is input. 2. open drain output: requires pullup resistor of 270 ? . master idt71321 easily expands data bus width to 16-or- more-bits using slave idt71421 on-chip port arbitration logic (idt71321 only) busy output flag on idt71321; busy input on idt71421 fully asynchronous operation from either port battery backup operation ? 2v data retention (la only) ttl-compatible, single 5v 10% power supply available in 52-pin plcc, 64-pin tqfp, and 64-pin stqfp industrial temperature range (?40c to +85c) is available for selected speeds green parts available, see ordering information i/o control address decoder memory array arbitration and interrupt logic address decoder i/o control r/ w l ce l oe l busy l a 10l a 0l 2691 drw 01 i/o 0l -i/o 7l ce l oe l r/ w l int l busy r i/o 0r -i/o 7r a 10r a 0r int r ce r oe r (2) (1,2) (1,2) (2) r/ w r ce r oe r r/ w r 11 11
6.42 idt71321sa/la and idt71421sa/la high speed 2k x 8 dual-port static ram with interrupts industrial and commercial temper ature ranges 2 idt71321/421j j52-1 (4) plcc top view (5) i ndex i/o a a a a a a a a a i/o i/o i/o 1l 2l 3l 4l 5l 6l 7l 8l 9l 0l 1l 3l 2l oe a a a a a a a a a a nc i/o r 0r 1r 2r 3r 4r 5r 6r 7r 8r 9r 7r 4 l 5 l 6 l 7 l n c g n d i / o i / o i / o i / o i / o i / o i / o i / o i / o i / o i / o 0 r 1 r 2 r 3 r 4 r 6 r 5 r a 0 l o e a i n t b u s y r / w c e v c e r / w b u s y i n t a l 1 0 l l l c c r r r 1 0 r r l l 1 2 3 4 5 6 747 48 49 50 51 52 9 8 10 11 12 13 14 15 16 17 18 19 20 27 26 25 24 23 22 21 33 32 31 30 29 28 35 34 36 37 38 39 40 41 42 43 44 45 46 2691 drw 02 , i ndex idt71321/421pf or tf pn64-1 / pp64-1 (4) 64-pin tqfp 64-pin stqfp top view (5) 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 46 45 44 43 42 41 40 39 38 37 36 35 34 47 48 33 i/o 6r n/c a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r i/o 7r oe r n/c n/c i/o 2l a 0l oe l a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l n/c n/c 2691 drw 03 1 7 1 8 1 9 2 0 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 4 9 5 0 5 1 5 2 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 6 4 n / c a 1 0 r n / c n / c a 1 0 l n / c g n d n / c n / c g n d n / c r / w r c e r v c c v c c b u s y l i n t l i / o 3 l i / o 4 l i / o 5 l i / o 6 l i / o 7 l i / o 0 r i / o 1 r i / o 2 r i / o 3 r i / o 4 r i / o 5 r r / w l c e l b u s y r i n t r , pin configurations (1,2,3) description the idt71321/idt71421 are high-speed 2k x 8 dual-port static rams with internal interrupt logic for interprocessor communications. the idt71321 is designed to be used as a stand-alone 8-bit dual- port static ram or as a "master" dual-port static ram together with the idt71421 "slave" dual-port in 16-bit-or-more word width systems. using the idt master/slave dual-port static ram ap- proach in 16-or-more-bit memory system applications results in full speed, error-free operation without the need for additional discrete logic. both devices provide two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power down feature, controlled by ce , permits the on chip circuitry of each port to enter a very low standby power mode. fabricated using idt's cmos high-performance technology, these devices typically operate on only 325mw of power. low-power (la) versions offer battery backup data retention capability, with each dual- port typically consuming 200w from a 2v battery. the idt71321/idt71421 devices are packaged in 52-pin plccs, 64-pin tqfps, and 64-pin stqfps. notes: 1. all v cc pins must be connected to power supply. 2. all gnd pins must be connected to ground supply. 3. j52-1 package body is approximately .75 in x .75 in x .17 in. pn64-1 package body is approximately 14mm x 14mm x 1.4mm. pp64-1 package body is approximately 10mm x 10mm x 1.4mm. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking.
6.42 idt71321sa/la and idt71421sa/la high speed 2k x 8 dual-port static ram with interrupts industrial and commercial temper ature ranges 3 recommended dc operating conditions absolute maximum ratings (1) recommended operating temperature and supply voltage (1,2) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v cc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > v cc + 10%. notes: 1. v il (min.) = -1.5v for pulse width less than 10ns. 2. v term must not exceed vcc + 10%. notes: 1. this is the parameter t a . this is the "instant on" case temperature. 2. industrial temperature: for specific speeds, packages and powers contact your sales office. symbol rating commercial & industrial unit v te rm (2) terminal voltage with re spe ct to gnd -0.5 to +7.0 v t bias te m p e r a tu re und er bias -55 to +125 o c t stg storage te m p e r a tu re -65 to +150 o c i out dc outp ut current 50 ma 2691 tbl 01 grade ambient temperature gnd vcc commercial 0 o c to +70 o c0v 5.0v + 10% industrial -40 o c to +85 o c0v 5.0v + 10% 2691 tbl 02 symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ____ 6.0 (2 ) v v il input low voltage -0.5 (1 ) ____ 0.8 v 2691 tbl 03 capacitance (1) (ta = +25c, f = 1.0mhz) tqfp only notes: 1. this parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0v to 3v or from 3v to 0v. symbol parameter conditions (2 ) max. unit c in input capacitance v in = 3dv 9 pf c out output capacitance v out = 3dv 10 pf 2691 tbl 00
6.42 idt71321sa/la and idt71421sa/la high speed 2k x 8 dual-port static ram with interrupts industrial and commercial temper ature ranges 4 dc electrical characteristics over the operating temperature and supply voltage range (1,4) (v cc = 5.0v 10%) notes: 1. 'x' in part numbers indicates power rating (sa or la). 2. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/t rc , and using ?ac test conditions? of input levels of gnd to 3v. 3. f = 0 means no address or control lines change. applies only to inputs at cmos level standby. 4. vcc = 5v, t a =+25c for typ and is not production tested. vcc dc = 100ma (typ) 5. port "a" may be either left or right port. port "b" is opposite from port "a". 71321x20 71421x20 com'l only 71321x25 71421x25 com'l & ind symbol parameter test condition version typ. max. typ. max. unit i cc dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled f = f max (2) com'l sa la 110 110 250 200 110 110 220 170 ma ind sa la ____ ____ ____ ____ 110 110 270 220 i sb1 standby current (both ports - ttl level inputs) ce l and ce r = v ih f = f max (2) com'l sa la 30 30 65 45 30 30 65 45 ma ind sa la ____ ____ ____ ____ 30 30 75 55 i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5 ) active port outputs disabled, f= f max (2 ) com'l sa la 65 65 165 125 65 65 150 115 ma ind sa la ____ ____ ____ ____ 65 65 170 140 i sb3 full standby current (both ports - cmos level inputs) ce l and ce r > v cc - 0.2v, v in > v cc - 0.2v or v in < 0.2v, f = 0 (3) com'l sa la 1.0 0.2 15 5 1.0 0.2 15 5 ma ind sa la ____ ____ ____ ____ 1.0 0.2 30 10 i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v cc - 0.2v (5 ) v in > v cc - 0.2v or v in < 0.2v active port outputs disabled, f = f max (2) com'l sa la 60 60 155 115 60 60 145 105 ma ind sa la ____ ____ ____ ____ 60 60 165 130 2691 tbl 04a 71321x35 71421x35 com'l only 71321x55 71421x55 com'l & ind symbol parameter test condition version typ. max. typ. max. unit i cc dynamic ope rating curre nt (both ports active) ce l and ce r = v il , outputs disabled f = f max (2 ) com'l sa la 80 80 165 120 65 65 155 110 ma ind sa la ____ ____ ____ ____ 65 65 190 140 i sb1 standby current (both ports - ttl level inputs) ce l and ce r = v ih f = f max (2 ) com'l sa la 25 25 65 45 20 20 65 35 ma ind sa la ____ ____ ____ ____ 20 20 70 50 i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5) active port outputs disabled, f=f max (2 ) com'l sa la 50 50 125 90 40 40 110 75 ma ind sa la ____ ____ ____ ____ 40 40 125 90 i sb3 full standby current (both ports - cmos level inputs) ce l and ce r > v cc - 0.2v, v in > v cc - 0.2v or v in < 0.2v, f = 0 (3 ) com'l sa la 1.0 0.2 15 4 1.0 0.2 15 4 ma ind sa la ____ ____ ____ ____ 1.0 0.2 30 10 i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v cc - 0.2v (5) v in > v cc - 0.2v o r v in < 0.2v active port outputs disabled, f = f max (2 ) com'l sa la 45 45 110 85 40 40 100 70 ma ind sa la ____ ____ ____ ____ 40 40 110 85 2691 tbl 04b
6.42 idt71321sa/la and idt71421sa/la high speed 2k x 8 dual-port static ram with interrupts industrial and commercial temper ature ranges 5 dc electrical characteristics over the operating temperature and supply voltage range (v cc = 5.0v 10%) note: 1. at vcc < 2.0v leakages are undefined. data retention characteristics (la version only) notes: 1. v cc = 2v, t a = +25c, and is not production tested. 2. t rc = read cycle time 3. this parameter is guaranteed but not production tested. data retention waveform v cc ce 4.5v 4.5v data retention mode t cdr t r v ih v ih v dr v dr 2.0v 2691 drw 04 , symbol parameter test conditions 71321sa 71421sa 71321la 71421la unit min. max. min. max. |i li | input leakage current (1 ) v cc = 5.5v, v in = 0v to v cc ___ 10 ___ 5a |i lo | output leakage current (1 ) ce = v ih , v out = 0v to v cc , v cc - 5.5v ___ 10 ___ 5a v ol output low voltage (i/o 0 -i/o 7 )i ol = 4ma ___ 0.4 ___ 0.4 v v ol open drain output low voltage ( busy / int ) i ol = 16ma ___ 0.5 ___ 0.5 v v oh output high voltage i oh = -4ma 2.4 ___ 2.4 ___ v 2691 tbl 05 symbol parameter test condition min. typ. (1 ) max. unit v dr v cc for data re te ntio n 2.0 ____ 0v i ccdr data retention current v cc = 2.0v, ce > v cc - 0.2v com'l ____ 100 1500 a v in > v cc - 0.2v or vi n < 0.2v ind ____ 100 4000 a t cd r (3 ) chip de se le ct to data re te ntio n time 0 ____ ____ ns t r (3 ) operation recovery time t rc (2) ____ ____ ns 2691 tb l 0 6
6.42 idt71321sa/la and idt71421sa/la high speed 2k x 8 dual-port static ram with interrupts industrial and commercial temper ature ranges 6 5v 1250 ? 30pf* 775 ? data out 5v 1250 ? 775 ? 5pf* data out 2691 drw 05 5v 270 ? 30pf* busy or int *100pf for 55ns versions *100pf for 55ns versions , figure 1. ac output test load figure 2. output test load (for t hz , t lz , t wz , and t ow ) * including scope and jig. figure 3. busy and int ac output test load ac test conditions input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 5ns 1.5v 1.5v figures 1,2 and 3 2691 tbl 07
6.42 idt71321sa/la and idt71421sa/la high speed 2k x 8 dual-port static ram with interrupts industrial and commercial temper ature ranges 7 notes: 1. transition is measured 0mv from low or high-impedance voltage output test load (figure 2). 2. 'x' in part numbers indicates power rating (sa or la). 3. this parameter is guaranteed by device characterization, but is not production tested. ac electrical characteristics over the operating temperature supply voltage range (2) 71321x20 71421x20 com'l only 71321x25 71421x25 com'l & ind unit symbol parameter min. max. min. max. read cycle t rc read cycle time 20 ____ 25 ____ ns t aa address access time ____ 20 ____ 25 ns t ace chip enable access time ____ 20 ____ 25 ns t aoe output enable access time ____ 11 ____ 12 ns t oh output hold from address change 3 ____ 3 ____ ns t lz outp ut lo w-z time (1,3) 0 ____ 0 ____ ns t hz output high-z time (1,3) ____ 10 ____ 10 ns t pu chip enable to power up time (3 ) 0 ____ 0 ____ ns t pd chip disable to power down time (3 ) ____ 20 ____ 25 ns 2 691 tbl 08a 71321x35 71421x35 com'l only 71321x55 71421x55 com'l & ind unit symbol parameter min. max. min. max. read cycle t rc read cycle time 35 ____ 55 ____ ns t aa address access time ____ 35 ____ 55 ns t ace chip enable access time ____ 35 ____ 55 ns t aoe output enable access time ____ 20 ____ 25 ns t oh output hold from address change 3 ____ 3 ____ ns t lz outp ut lo w-z time (1,3) 0 ____ 5 ____ ns t hz output high-z time (1,3) ____ 15 ____ 25 ns t pu chip enable to power up time (3 ) 0 ____ 0 ____ ns t pd chip disable to power down time (3 ) ____ 35 ____ 50 ns 2691 tbl 08b
6.42 idt71321sa/la and idt71421sa/la high speed 2k x 8 dual-port static ram with interrupts industrial and commercial temper ature ranges 8 timing waveform of read cycle no. 2, either side (3) notes: 1. timing depends on which signal is asserted last, oe or ce . 2. timing depends on which signal is de-asserted first, oe or ce . 3. r/ w = v ih and oe = v il , and the address is valid prior to or coincidental with ce transition low. 4. start of valid data depends on which timing becomes effective last t aoe , t ace , t aa , and t bdd . timing waveform of read cycle no. 1, either side (1) notes: 1. r/ w = v ih , ce = v il , and is oe = v il . address is valid prior to the coincidental with ce transition low. 2. t bdd delay is required only in the case where the opposite port is completing a write operation to the same address location. for s imultaneous read operations busy has no relationship to valid output data. 3. start of valid data depends on which timing becomes effective last t aoe , t ace , t aa , and t bdd . address data out t rc t oh previous data valid t aa t oh data valid 2691 drw 06 t bddh (2,3) busy out ce t ace t aoe t hz t lz t pd valid data t pu 50% oe data out current i cc i ss 50% 2691 drw 07 (4) (1) (1) (2) (2) (4) t lz t hz
6.42 idt71321sa/la and idt71421sa/la high speed 2k x 8 dual-port static ram with interrupts industrial and commercial temper ature ranges 9 ac electrical characteristics over the operating temeprature and supply voltage range (4) notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 2). this parameter is guaranteed by device characterization but is not production tested. 2. for master/slave combination, t wc = t baa + t wp , since r/ w = v il must occur after t baa . 3. if oe is low during a r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off data to be placed on the bus for the required t dw . if oe is high during a r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . 4. 'x' in part numbers indicates power rating (sa or la). symbol parameter 71321x20 71421x20 com'l only 71321x25 71421x25 com'l & ind unit min. max. min. max. writ e cycle t wc write cycle time (2 ) 20 ____ 25 ____ ns t ew chip enable to end-of-write 15 ____ 20 ____ ns t aw address valid to end-of-write 15 ____ 20 ____ ns t as address set-up time 0 ____ 0 ____ ns t wp write pulse width (3 ) 15 ____ 15 ____ ns t wr write recovery time 0 ____ 0 ____ ns t dw data valid to end-of-write 10 ____ 12 ____ ns t hz output high-z time (1) ____ 10 ____ 10 ns t dh data ho ld time 0 ____ 0 ____ ns t wz write enable to output in high-z (1) ____ 10 ____ 10 ns t ow output active from end-of-write (1 ) 0 ____ 0 ____ ns 2 691 tbl 09a symbol parameter 71321x35 71421x35 com'l only 71321x55 71421x55 com'l & ind unit min. max. min. max. writ e cycle t wc write cycle time (2 ) 35 ____ 55 ____ ns t ew chip enable to end-of-write 30 ____ 40 ____ ns t aw address valid to end-of-write 30 ____ 40 ____ ns t as address set-up time 0 ____ 0 ____ ns t wp write pulse width (3 ) 25 ____ 30 ____ ns t wr write recovery time 0 ____ 0 ____ ns t dw data valid to end-of-write 15 ____ 20 ____ ns t hz output high-z time (1) ____ 15 ____ 25 ns t dh data ho ld time 0 ____ 0 ____ ns t wz write enable to output in high-z (1) ____ 15 ____ 30 ns t ow output active from end-of-write (1 ) 0 ____ 0 ____ ns 2691 tbl 09b
6.42 idt71321sa/la and idt71421sa/la high speed 2k x 8 dual-port static ram with interrupts industrial and commercial temper ature ranges 10 timing waveform of write cycle no. 2, ( ce controlled timing) (1,5) timing waveform of write cycle no. 1, (r/ w controlled timing) (1,5,8) notes: 1. r/ w or ce must be high during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of ce = v il and r/w= v il . 3. t wr is measured from the earlier of ce or r/ w going high to the end of the write cycle. 4. during this period, the l/o pins are in the output state and input signals must not be applied. 5. if the ce low transition occurs simultaneously with or after the r/ w low transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal ( ce or r/ w ) is asserted last. 7. this parameter is determined to be device characterization, but is not production tested. transition is measured 0mv from ste ady state with the output test load (figure 2). 8. if oe is low during a r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off data to be placed on the bus for the required t dw . if oe is high during a r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . address oe ce r/ w data out data in (4) (4) 2691 drw 08 t wc t as (6) t wr (3) t ow t dw t dh t aw t wp (2) t hz (7) t wz (7) t hz (7) t wc address ce r/ w data in t as (6) t ew (2) t wr t dw t dh t aw 2691 drw 09 (3)
6.42 idt71321sa/la and idt71421sa/la high speed 2k x 8 dual-port static ram with interrupts industrial and commercial temper ature ranges 11 ac electrical characteristics over the operating temperature and supply voltage range (6) notes: 1. port-to-port delay through ram cells from the writing port to the reading port, refer to ?timing waveform of write with port- to-port read and busy." 2. to ensure that the earlier of the two ports wins. 3. t bdd is a calculated parameter and is the greater of 0, t wdd ? t wp (actual) or t ddd ? t dw (actual). 4. to ensure that a write cycle is inhibited on port "b" during contention on port "a". 5. to ensure that a write cycle is completed on port "b" after contention on port "a". 6. 'x' in part numbers indicates power rating (sa or la).. 71321x20 71421x20 com'l only 71321x25 71421x25 com'l & ind symbol parameter min.max.min.max.unit busy timing (for master 71321) t baa busy access time from address ____ 20 ____ 20 ns t bda busy disable time from address ____ 20 ____ 20 ns t ba c busy access time from chip enable ____ 20 ____ 20 ns t bdc busy disable time from chip enable ____ 20 ____ 20 ns t wh write hold after busy (5) 12 ____ 15 ____ ns t wdd write pulse to data delay (1) ____ 50 ____ 50 ns t dd d write data valid to read data delay (1) ____ 35 ____ 35 ns t ap s arbitration priority set-up time (2 ) 5 ____ 5 ____ ns t bdd busy disable to valid data (3) ____ 25 ____ 35 ns busy input timing (for slave 71421) t wb write to busy input (4) 0 ____ 0 ____ ns t wh write hold after busy (5) 12 ____ 15 ____ ns t wdd write pulse to data delay (1) ____ 40 ____ 50 ns t dd d write data valid to read data delay (1) ____ 30 ____ 35 ns 2691 tbl 10a 71321x35 71421x35 com'l only 71321x55 71421x55 com'l & ind symbol parameter min.max.min.max.unit busy timing (for master 71321) t baa busy access time from address ____ 20 ____ 30 ns t bda busy disable time from address ____ 20 ____ 30 ns t ba c busy access time from chip enable ____ 20 ____ 30 ns t bdc busy disable time from chip enable ____ 20 ____ 30 ns t wh write hold after busy (5) 20 ____ 20 ____ ns t wdd write pulse to data delay (1) ____ 60 ____ 80 ns t dd d write data valid to read data delay (1) ____ 35 ____ 55 ns t ap s arbitration priority set-up time (2 ) 5 ____ 5 ____ ns t bdd busy disable to valid data (3) ____ 35 ____ 50 ns busy input timing (for slave 71421) t wb write to busy input (4) 0 ____ 0 ____ ns t wh write hold after busy (5) 20 ____ 20 ____ ns t wdd write pulse to data delay (1) ____ 60 ____ 80 ns t dd d write data valid to read data delay (1) ____ 35 ____ 55 ns 2691 tbl 10b
6.42 idt71321sa/la and idt71421sa/la high speed 2k x 8 dual-port static ram with interrupts industrial and commercial temper ature ranges 12 t wc t wp t dw t dh t bdd t ddd t bda t wdd addr "b" d ata out"b" data in "a" addr "a" match valid match valid r/ w "a" busy "b" t aps (1) 2691 drw 10 t baa timing waveform of write with port-to-port read and busy (2,3,4) notes: 1. to ensure that the earlier of the two ports wins. t aps is ignored for slave (idt71421). 2. ce l = ce r = v il 3. oe = v il for the reading port. 4. all timing is the same for the left and right ports. port "a" may be either the left or right port. port "b" is opposite from port "a". notes: 1. t wh must be met for both busy input (idt71421, slave) or output (idt71321, master). 2. busy is asserted on port "b" blocking r/ w "b" , until busy "b" goes high. 3. t wb is only for the slave version (idt71421). 4. all timing is the same for the left and right ports. port "a" may be either the left or right port. port "b" is opposite from port "a". timing waveform of write with busy (4) busy "b" 2691 drw 11 r/ w "a" t wp t wh t wb r/ w "b" (2) (1) (3) ,
6.42 idt71321sa/la and idt71421sa/la high speed 2k x 8 dual-port static ram with interrupts industrial and commercial temper ature ranges 13 timing waveform of busy arbitration controlled by ce timing (1) timing waveform of busy arbritration controlled by address match timing (1) notes: 1. all timing is the same for left and right ports. port ?a? may be either left or right port. port ?b? is the opposite from por t ?a?. 2. if t aps is not satisified, the busy will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted (idt71321 only). ac electrical characteristics over the operating temperature and supply voltage range (1) notes: 1. 'x' in part numbers indicates power rating (sa or la). t aps (2) addr "a" and "b" addresses match t bac t bdc ce "b" ce "a" busy "a" 2691 drw 12 busy "b" addresses do not match addresses match t aps (2) addr "a" addr "b" 2691 drw 13 t baa t bda t rc or t wc 71321x20 71421x20 com'l only 71321x25 71421x25 com'l & ind symbol parameter min. max. min. max. unit interrupt timing t as address set-up time 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ ns t ins inte rrupt set time ____ 20 ____ 25 ns t inr inte rrupt re se t time ____ 20 ____ 25 ns 2691 tbl 11 a
6.42 idt71321sa/la and idt71421sa/la high speed 2k x 8 dual-port static ram with interrupts industrial and commercial temper ature ranges 14 timing waveform of interrupt mode (1) set int clear int notes: 1. all timing is the same for left and right ports. port ?a? may be either left or right port. port ?b? is the opposite from po rt ?a?. 2. see interrupt truth table. 3. timing depends on which enable signal ( ce or r/ w ) is asserted last. 4. timing depends on which enable signal ( ce or r/ w ) is de-asserted first. ac electrical characteristics over the operating temperature supply voltage range (1) notes: 1. 'x' in part numbers indicates power rating (sa or la). t ins addr "a" int "b" interrupt address t wc t as r/ w "a" t wr 2691 drw 14 (3) (3) (2) (4) t rc interrupt clear address a ddr "b" oe "b" t inr int "b" 2691 drw 15 t as (3) (3) (2) , 71321x35 71421x35 com'l only 71321x55 71421x55 com'l & ind symbol parameter min. max. min. max. unit interrupt timing t as address set-up time 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ ns t ins inte rrupt se t time ____ 25 ____ 45 ns t inr interrupt reset time ____ 25 ____ 45 ns 2691 tbl 11b
6.42 idt71321sa/la and idt71421sa/la high speed 2k x 8 dual-port static ram with interrupts industrial and commercial temper ature ranges 15 truth table iii ? address busy arbitration truth table i. non-contention read/write control (4) notes: 1. pins busy l and busy r are both outputs for idt71321 (master). both are inputs for idt71421 (slave). busy x outputs on the idt71321 are open drain, not push- pull outputs. on slaves the busy x input internally inhibits writes. 2. 'l' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'h' if the inputs to the opposite port became stable after the address and enable inputs of this port. if t aps is not met, either busy l or busy r = low will result. busy l and busy r outputs can not be low simultaneously. 3. writes to the left port are internally ignored when busy l outputs are driving low regardless of actual logic level on the pin. writes to the right port are internally ignored when busy r outputs are driving low regardless of actual logic level on the pin. truth tables truth table ii. interrupt flag (1,4) notes: 1. a 0l ? a 10l a 0r ? a 10r . 2. if busy = l, data is not written. 3. if busy = l, data may not be valid, see t wdd and t ddd timing. 4. 'h' = v ih , 'l' = v il , 'x' = don?t care, 'z' = high impedance notes : 1. assumes busy l = busy r = v ih 2. if busy l = v il , then no change. 3. if busy r = v il , then no change. 4. 'h' = high, 'l' = low, 'x' = don?t care left or right port (1) function r/ w ce oe d 0-7 x h x z port disabled and in power-down mode, isb 2 or isb 4 xhx z ce r = ce l = v ih , power-down mode, isb 1 or isb 3 llxdata in data on port written into memory (2 ) hl ldata out data in memory output on por t (3 ) h l h z high impedance outputs 2691 tbl 12 left port right port function r/ w l ce l oe l a 10l -a 0l int l r/ w r ce r oe r a 10r -a 0r int r llx7ffxxxx x l (2 ) se t rig ht int r flag xxxxxxll7ff h (3) re se t right int r flag xxx x l (3 ) l l x 7fe x se t left int l flag xll7fe h (2 ) x x x x x re se t left int l flag 2691 tbl 13 inputs outputs function ce l ce r a 0l -a 10l a 0r -a 10r busy l (1 ) busy r (1) xxno match h h normal hx match h h normal xh match h h normal l l match (2) (2) write inhibit (3 ) 2691 tbl 14
6.42 idt71321sa/la and idt71421sa/la high speed 2k x 8 dual-port static ram with interrupts industrial and commercial temper ature ranges 16 being expanded in depth, then the busy indication for the resulting array does not require the use of an external and gate. width expansion with busy logic master/slave arrays when expanding an sram array in width while using busy logic, one master part is used to decide which side of the sram array will receive a busy indication, and to output that indication. any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. thus on the idt71321/idt71421 srams the busy pin is an output if the part is master (idt71321), and the busy pin is an input if the part is a slave (idt71421) as shown in figure 3. if two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. this would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. the busy arbitration, on a master, is based on the chip enable and address signals only. it ignores whether an access is a read or write. in a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with either the r/ w signal or the byte enables. failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. functional description the idt71321/idt71421 provides two ports with separate control, address and i/o pins that permit independent access for reads or writes to any location in memory. the idt71321/idt71421 has an automatic power down feature controlled by ce . the ce controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce = v ih ). when a port is enabled, access to the entire memory array is permitted. interrupts if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is asserted when the right port writes to memory location 7fe (hex), where a write is defined as the ce r = r/ w r = v il, per truth table ii. the left port clears the interrupt by accessing address location 7fe when ce l = oe l = v il, r/w is a "don't care". likewise, the right port interrupt flag ( int r ) is asserted when the left port writes to memory location 7ff (hex) and to clear the interrupt flag ( int r ), the right port must access the memory location 7ff. the message (8 bits) at 7fe or 7ff is user-defined, since it is an addressable sram location. if the interrupt function is not used, address locations 7fe and 7ff are not used as mail boxes, but as part of the random access memory. refer to truth table ii for the interrupt operation. busy logic busy logic provides a hardware indication that both ports of the ram have accessed the same location at the same time. it also allows one of the two accesses to proceed and signals the other side that the ram is ?busy?. the busy pin can then be used to stall the access until the operation on the other side is completed. if a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. the use of busy logic is not required or desirable for all applications. in some cases it may be useful to logically or the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. in slave mode the busy pin operates solely as a write inhibit input pin. normal operation can be programmed by tying the busy pins high. if desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. the busy outputs on the idt71321 (master) are open drain type outputs and require open drain resistors to operate. if these srams are figure 3. busy and chip enable routing for both width and depth expansion with idt71321 (master) and (slave) idt71421 srams. 2691 drw 16 master dual port sram busy l busy r ce master dual port sram busy l busy r ce slave dual port sram busy l busy r ce slave dual port sram busy l busy r ce busy l busy r d e c o d e r 5v 5v 270 ? 2 70 ? ,
6.42 idt71321sa/la and idt71421sa/la high speed 2k x 8 dual-port static ram with interrupts industrial and commercial temper ature ranges 17 ordering information notes: 1. contact your sales office for industrial temperature range availability in other speeds, packages and powers. 2. green parts available. for specific speeds, packages and powers contact your local sales office. 52-pin plcc (j52-1) 64-pin tqfp (pn64-1) 64-pin stqfp (pp64-1) xxxx device type a 999 aa power speed package process/ temperature range 71321 71421 16k (2k x 8-bit) master dual-port sram w/ interrupt 16k (2k x 8-bit) slave dual-port sram w/ interrupt speed in nanoseconds 2691 drw 17 blank i (1) j pf tf 20 25 35 55 la sa commercial (0c to +70c) industrial (-40c to +85c) low power standard power commercial only commercial & industrial commercial only commercial & industrial , a g green (2) datasheet document history 03/24/99: initiated datasheet document history converted to new format cosmetic typographical corrections pages 2 and 3 added additional notes to pin configurations 06/07/99: changed drawing format 11/10/99: replaced idt logo 08/23/01: page 3 increased storage temperature parameters clarified t a parameter page 4 dc electrical parameters?changed wording from "open" to "disabled" page 16 fixed part numbers in "width expansion" paragraph changed 500mv to 0mv in notes page 4 industrial temperature range offering added to dc electrical characteristisc for 25ns and removed for 35ns page 7 and 9 industrial temperature range added to ac electrical characteristics for 25ns page 17 industrial offering removed for 35ns ordering information 01/17/06: page 1 added green availability to features page 17 added green indicator to ordering information page 1 & 17 replaced old idt tm with new idt tm logo 08/25/06: page 14 changed int "a" to int "b" in the clear int drawing in the timing waveform of interrupt mode 10/29/08: page 17 removed "idt" from orderable part number the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com

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